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? july 2002 1/22 vn800s(8961) / VN800PT(8961) high side driver n cmos compatible input n thermal shutdown n current limitation n shorted load protection n undervoltage and overvoltage shutdown n protection against loss of ground n very low stand-by current n reverse battery protection (*) description the vn800s(8961), VN800PT(8961) are monolithic devices made by using stmicroelectronics vipower m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). active current limitation combined with thermal shutdown and automatic restart protect the device against overload. device automatically turns off in case of ground pin disconnection. type r ds(on) i out v cc vn800s(8961) VN800PT(8961) 135 m w 1.2 a 36 v so-8 ppak order codes package tube t&r so-8 vn800s(8961) vn800s(8961)tr ppak VN800PT(8961) VN800PT(8961) tr block diagram undervoltage overtemperature gnd input output overvoltage current limiter logic driver power clamp status v cc clamp detection detection detection (*) see note at page 8 v cc
2/22 vn800s(8961) / VN800PT(8961) absolute maximum rating connection diagram (top view) current and voltage conventions symbol parameter value unit so-8 ppak v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 6 a i in dc input current +/- 10 ma v in input voltage range -3/+v cc v v stat dc status voltage + v cc v v esd electrostatic discharge (human body model: r=1.5k w ; c=100pf) - input - status - output - v cc 4000 4000 5000 5000 v v v v e max maximum switching energy (l=77.5mh; r l =0 w ; v bat =13.5v; t jstart =150oc; i l =1.5a) 121 mj e max maximum switching energy (l=125mh; r l =0 w ; v bat =13.5v; t jstart =150oc; i l =1.5a) 195 mj p tot power dissipation t c =25c 4.2 41.7 w t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 c l max max inductive load (v cc =30v; r load =48 w ; t amb =100c; rth case>ambient 25c/w) 2h v cc v cc output output n.c. gnd status input 1 4 5 8 5 4 3 2 1 status output gnd input v cc so-8 ppak input i s i in v in v cc status i stat v stat gnd v cc i out v out i gnd output
3/22 vn800s(8961) / VN800PT(8961) thermal data (*) when mounted on fr4 printed circuit board with 0.5 cm 2 of copper area (at least 35 m thick) connected to all v cc pins. (**) when mounted on fr4 printed circuit board with 0.5 cm 2 of copper area (at least 35 m thick). electrical characteristics (8v 4/22 vn800s(8961) / VN800PT(8961) 2 electrical characteristics (continued) status pin protections symbol parameter test conditions min typ max unit v stat status low output voltage i stat =1.6 ma 0.5 v i lstat status leakage current normal operation; v stat =v cc =36 v 10 m a c stat status pin input capacitance normal operation; v stat = 5v 30 pf symbol parameter test conditions min typ max unit t tsd shut-down temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl status delay in overload condition t j >t jsh 20 m s i lim dc short circuit current v cc =16v; r load =10m w 1.2 2 a v demag turn-off output clamp voltage i out =0.5 a; l=6mh v cc -47 v cc -52 v cc -57 v overtemp status timing t j >t jsh v in v stat t sdl t sdl
5/22 vn800s(8961) / VN800PT(8961) v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) t d(off) t d(on) v in t t 90% switching time waveforms truth table conditions input output status normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l overtemperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h
6/22 vn800s(8961) / VN800PT(8961) figure 1: peak short circuit current test circuit figure 2: avalanche energy test circuit 10k w control unit r in input gnd output r l =10m w + v cc gnd status 10k w control unit r in input gnd output load + v cc gnd status v cc v cc
7/22 vn800s(8961) / VN800PT(8961) iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 w 2 +25 v +50 v +75 v +100 v 0.2 ms 10 w 3a -25 v -50 v -100 v -150 v 0.1 m s 50 w 3b +25 v +50 v +75 v +100 v 0.1 m s 50 w 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 w 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 w iso t/r 7637/1 test pulse test levels results iiiiiiiv 1cccc 2cccc 3acccc 3bcccc 4cccc 5ceee electrical transient requirements on v cc pin class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
8/22 vn800s(8961) / VN800PT(8961) gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd 3 (- v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the devices datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k w) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. m c i/os protection: if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the m c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of m c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of m c i/os. -v ccpeak /i latchup r prot (v oh m c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 3 20ma; v oh m c 3 4.5v 5k w r prot 65k w . recommended r prot value is 10k w. application schematic v cc input gnd st atus output vol t . reg bus asi c 5v 24vdc v cc dgnd vgnd rgnd rprot rprot load r l d id control & diagnostic i/o
9/22 vn800s(8961) / VN800PT(8961) status input normal operation undervoltage v cc v usd v usdhyst input overvoltage v cc v cc >v ov status input status undefined figure 3: waveforms load voltage v cc 10/22 vn800s(8961) / VN800PT(8961) high level input current status leakage current off state output current -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 1 2 3 4 5 6 7 8 iih (a) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 ilstat (a) vstat=vcc=36v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 il(off1) (a) off state vcc=36v vin=vout=0v on state resistance vs t case on state resistance vs v cc -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 50 100 150 200 250 300 350 400 ron (mohm) iout=0.5a vcc=8v; 13v; 36v 5 10152025303540 vcc (v) 0 50 100 150 200 250 300 350 400 ron (mohm) iout=0.5a tc= - 40oc tc= 25oc tc= 150oc i lim vs t case -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 ilim (a) vcc=24v rl=10mohm
11/22 vn800s(8961) / VN800PT(8961) 1 input hysteresis voltage input low level input high level -50 -25 0 25 50 75 100 125 150 175 tc (c) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v) overvoltage shutdown -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) turn-on voltage slope turn-off voltage slope -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 200 400 600 800 1000 1200 1400 1600 dvout/dt(on) (v/ms) vcc=24v rl=48ohm -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 100 200 300 400 500 600 700 800 dvout/dt(off) (v/ms) vcc=24v rl=48ohm
12/22 vn800s(8961) / VN800PT(8961) ppak maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. v in , i l t demagnetization demagnetization demagnetization 0.1 1 10 1 10 100 1000 l(mh) i lmax (a) a b c
13/22 vn800s(8961) / VN800PT(8961) so-8 maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. v in , i l t demagnetization demagnetization demagnetization 0.1 1 10 1 10 100 1000 l(mh) i lmax (a) a b c
14/22 vn800s(8961) / VN800PT(8961) so-8 pc board r thj-amb vs pcb copper area in open box free air condition so-8 thermal data layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: 0.14cm 2 , 2cm 2 ). 70 75 80 85 90 95 100 105 110 00.511.522.5 pcb cu heatsink area (cm^2) rthj_ amb (oc/w ) so8 at 2 pins connected to tab
15/22 vn800s(8961) / VN800PT(8961) ppak pc board r thj-amb vs pcb copper area in open box free air condition ppak thermal data layout condition of r th and z th measurements (pcb fr4 area= 60mm x 60mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: 0.44cm 2 , 8cm 2 ). 0 10 20 30 40 50 60 70 80 90 0246810 pcb cu heatsink area (cm^2) rthj_amb (oc/w)
16/22 vn800s(8961) / VN800PT(8961) thermal fitting model of a single channel hsd in ppak pulse calculation formula thermal parameter area/island (cm 2 )0.446 r1 (c/w) 0.04 r2 (c/w) 0.25 r3 ( c/w) 0.3 r4 (c/w) 2 r5 (c/w) 15 r6 (c/w) 61 24 c1 (w.s/c) 0.0008 c2 (w.s/c) 0.007 c3 (w.s/c) 0.02 c4 (w.s/c) 0.3 c5 (w.s/c) 0.45 c6 (w.s/c) 0.8 5 z th d r th d z thtp 1 d C () + = where d t p t = ppak thermal impedance junction ambient single pulse t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) 0.44 cm 2 6 cm 2
17/22 vn800s(8961) / VN800PT(8961) thermal fitting model of a single channel hsd in so-8 pulse calculation formula thermal parameter area/island (cm 2 )0.142 r1 (c/w) 0.24 r2 (c/w) 1.2 r3 ( c/w) 4.5 r4 (c/w) 21 r5 (c/w) 16 r6 (c/w) 58 28 c1 (w.s/c) 0.00015 c2 (w.s/c) 0.0005 c3 (w.s/c) 7.50e-03 c4 (w.s/c) 0.045 c5 (w.s/c) 0.35 c6 (w.s/c) 1.05 2 z th d r th d z thtp 1 d C () + = where d t p t = so-8 thermal impedance junction ambient single pulse t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zt h (c /w) 0.5 cm 2 2 cm 2
18/22 vn800s(8961) / VN800PT(8961) dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.019 c1 45 (typ.) d 4.8 5 0.188 0.196 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 f 3.8 4 0.14 0.157 l 0.4 1.27 0.015 0.050 m 0.6 0.023 s 8 (max.) l1 0.8 1.2 0.031 0.047 so-8 mechanical data
19/22 vn800s(8961) / VN800PT(8961) dim. min. typ max. a 2.20 2.40 a1 0.90 1.10 a2 0.03 0.23 b 0.40 0.60 b2 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 d1 5.1 d 6.00 6.20 e 6.40 6.60 e1 4.7 e1.27 g 4.90 5.25 g1 2.38 2.70 h 9.35 10.10 l2 0.8 1.00 l4 0.60 1.00 r0.2 v2 0o 8o package weight gr. 0.3 ppak mechanical data p032t1
20/22 vn800s(8961) / VN800PT(8961) so-8 tube shipment (no suffix) all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a 3.2 b 6 c ( 0.1) 0.6 tape and reel shipment (suffix 13tr) all dimensions are in mm. base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions c b a
21/22 vn800s(8961) / VN800PT(8961) ppak tube shipment (no suffix ) 1 all dimensions are in mm. base q.ty 75 bulk q.ty 3000 tube length ( 0.5) 532 a 6 b 21.3 c ( 0.1) 0.6 tape and reel shipment (suffix 13tr) all dimensions are in mm. base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 16.4 n (min) 60 t (max) 22.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 16 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 7.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions a c b
22/22 vn800s(8961) / VN800PT(8961) information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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